1. Field of the Invention
The present invention relates to write protocols for memory accesses and, more specifically, to an optimized protocol for writing to memories having a fast paged mode memory access capability.
2. Description of the Related Art
Computer architects have long struggled to over come the data transfer bottleneck which has plagued von Neumann architectures. For example, cache memories have been utilized to store information in high speed memories allowing faster access to such information by a processor. Also, DRAM memory devices have improved technologically in density, in speed, and by offering additional modes for accessing data.
In a typical instruction stream the ratio of read accesses to write accesses is on the order of 4:1. Thus, a main memory subsystem must optimize the read transfer rate to provide for optimal performance. However, in a system utilizing a write-through cache memory, the ratio of read accesses to write accesses from main memory has decreased and in such systems, it is important to consider optimal performance of write accesses as well as read accesses. One known method of providing for optimal write accesses is through "posting" of write accesses. This is a process in which a write access is initiated on a system bus by a processor and then the processor is freed to execute other instructions without the need to wait for the completion of the write access to main memory.
The present invention relates to systems utilizing known standard RAS/CAS memory access methods. These methods are well known to one of ordinary skill in the art and essentially may be described as a memory access method in which a row address is provided on a bus to a memory device and a row address strobe (RAS) line is activated when the row address is available for the memory. Similarly, a column address is provided on the bus and a column address strobe is activated when the column address is available for the memory. At completion of the memory access, the RAS and CAS lines are deactivated. At this time the row address lines and column address lines may be precharged in preparation for the next memory access. As is understood, if there is a pending access request, overhead is incurred while waiting for precharge of the RAS and CAS lines. Standard RAS/CAS memory accesses are described in greater detail below with reference to FIG. 2.
One known variation of the standard RAS/CAS memory access scheme is termed "fast paged mode". In fast paged mode, the RAS line is deactivated only when a subsequent memory access is to a different memory page (i.e., row address) than the first memory access or when a memory refresh cycle occurs. Fast paged mode avoids overhead associated with precharging RAS lines prior to accessing the memory device where the subsequent access is to the same row address. Fast paged mode is described in greater detail with reference to FIG. 3.
In most applications, the RAS line, once activated, remains activated even if the bus is idle in anticipation of a DRAM page hit from a subsequent access. As will be appreciated from the Detailed Description of the Preferred Embodiment, the present invention utilizes an improved protocol to access DRAM memory in which the RAS line is held active only if another access is pending and the access is a hit to the same DRAM page as the immediately previous access. In all other cases the RAS line is deactivated.
This application also relates to co-pending U.S. patent application Ser. No. 07/292,476 filed Dec. 30, 1988, titled Request/Response Protocol which is assigned to the assignee of the present invention (the '476 reference) now abandoned. The present application further relates to U.S. patent application Ser. No. 07/292,566 filed Dec. 30, 1988, titled Self-identification of Memory which is assigned to the assignee of the present application (the '566 reference) now abandoned. Finally, the present application relates to U.S. patent application Ser. No. 07/403,174 filed Sep. 5, 1989, now U.S. Pat. No. 5,239,638 titled Two Strobed Memory Access which is assigned to the assignee of the present invention (the '174 reference) and which is a continuation of U.S. patent application Ser. No. 07/292,476. The teachings of the '476 reference, the '566 reference, and the '174 reference are all incorporated herein by reference.